A 17.7-42.9-GHz Low Power Low Noise Amplifier with 83% Fractional Bandwidth for Radio Astronomical Receivers in 65-nm CMOS

A 17.7-42.9-GHz low-power CMOS low noise amplifier (LNA) for radio astronomical receivers in 65-nm CMOS technology is presented in this paper. Based on several bandwidth enhancement techniques, the proposed LNA achieves high gain, good noise Figure simultaneously in a wide frequency range while consuming low power. The LNA achieves the 20.1-dB peak gain, and the noise Figure (NF) between 2.8 and 4.3 dB within the 3-dB bandwidth covering 17.7 to 42.9 GHz. The dc power consumption of this design is only 18 mW, while the OP 1dB is 2.2 dBm at 28GHz. The figure-of-merit (FOM) of this work is 19 GHz/mW, which reveals the competitiveness among published K-band and Ka-band LNAs. The whole chip occupies 0.45 mm2 including pads.