Design Transformation from a Single-Core to a Multi-Core Architecture Targeting Massively Parallel Signal Processing Algorithms

This chapter describes single-core and multi-core platforms that are reconfigurable and heterogeneous by design and are specifically targeted to accelerate computationally intensive signal processing algorithms mostly used in software-designed radio applications. The signal-core accelerator architectures are tightly integrated with a C programmable processor core while the backbone of communications and control in multi-core architecture is a network-on-chip. The platforms were instantiated multiple times for different proof-of-concept application scenarios. The single- and multi-core platforms were subjected to self-aware dynamic frequency scaling while being prototyped for a field programmable gate array device. The performance of the platforms was measured and estimated in terms of many basic and high-level metrics and comparisons with other state-of-the-art platform are established for design evaluation.