Key optimization techniques in JPEG-LS IP core design

This paper presents the key optimization techniques for an efficient accelerator implementation in an image encoder IP core design for real-time Joint Photographic Experts Group Lossless (JPEG-LS) encoding. Pipeline architecture and accelerator elements have been utilized to enhance the throughput capability. Improved parameters mapping schemes and resource sharing have been adopted for the purpose of low complexity and small chip die area. Module-level and fine-grained gating measures have been used to achieve a low-power implementation. It has been proved that these hardware-oriented optimization techniques make the encoder meet the requirements of the IP core implementation. The proposed optimization techniques have been verified in the implementation of the JPEG-LS encoder IP, and then validated in a real wireless endoscope system.