Design and Analysis of Low Power and Area Efficient Single Capacitor DAC Based Successive Approximation ADC Using 45 Nm Fin FET

Inherent suppression of short channel effects, reduced sub-threshold and gate-dielectric leakage, good scalability and ease of integration in analog, digital and RF circuits makes SOI Fin FET an important device for mixed signal and system on chip (SoC) solutions. In this work we carry out the feasibility study of Fin FET transistor for analog to digital converter (ADC) design. This paper, for the first time, presents an 8 bit, single switch-capacitor DAC SAR ADC design in 45 nm SOI double gate Fin FET technology and benchmarks the simulation results with similar design in 90 nm bulk CMOS. Shorted gate (SG) Fin FET design is utilized in regulated clocked current mirror, sampling unit and SAR control circuitry where maximum drive strength is required. The option to separately bias the two gates of Fin FET and operate them independently has been utilized in comparator design to reduce the power dissipation at higher conversion speed. Therefore at 1 V supply and 909 kS/s, this new ADC consumes only 9 a#x03BC;W of power, making it an area efficient design suitable for low-power low-cost VLSI applications.