See-through-silicon inspection application studies based on traditional silicon imager

With semiconductor development processes hitting harder and harder on Moore's law to continuously scale down, high density advanced packaging technologies become a promising alternate route to improve transistor density. Chip integration IO/cm 2 density jumps quickly by orders from 2D packaging of 10 2 to wire bonded chip stack of 10 3 , to TSV of 104~105 and to advanced 3D integration of 10 5 to 10 6 . Starting with wire bonding and now prevailing with TSV, more and more silicon layers are stacked up in 3D dimension to improve system density. A typical stacked wafer sample has two wafers glued together with patterned area sandwiched in between. Outer surfaces can be polished or unpolished bare silicon surface, or patterned surface.