Backend process for cylindrical Ru/Ta/sub 2/O/sub 5//Ru capacitor for future DRAM

A novel backend process is developed for the cylindrical Ru/Ta/sub 2/O/sub 5//Ru capacitor for 130 nm generation DRAMs to achieve good electrical characteristics. Forming gas (3%H/sub 2//97%N/sub 2/) anneal (FGA) induced degradation can be effectively suppressed. For the cylindrical Ru/Ta/sub 2/O/sub 5//Ru capacitor with full backend processes, including passivation layer formation and a FGA, the cell leakage current and cell capacitance are 1 fA (at /spl plusmn/0.8 V at 85/spl deg/C) and 15fF, respectively.