Old Web
English
Sign In
Acemap
>
Paper
>
Redundancy Circuit for a Sub-nanosecond, Megabit ECL-CMOS SRAM
Redundancy Circuit for a Sub-nanosecond, Megabit ECL-CMOS SRAM
1996
Kenichi Ohhata
Takeshi Kusunoki
Hiroaki Nambu
Kazuo Kanetani
Toru Masuda
Masayuki Ohayashi
Satomi Hamamoto
Kunihiko Yamaguchi
Youji Idei
Noriyuki Homma
Keywords:
Electronic engineering
Nanosecond
Redundancy (engineering)
Megabit
Engineering
BiCMOS
Static random-access memory
CMOS
Correction
Source
Cite
Save
Machine Reading By IdeaReader
0
References
1
Citations
NaN
KQI
[]