A 5 ps resolution, 8.6 ns delay range digital delay line using combinatorial redundancy

A novel digital delay line architecture is presented, which is able to achieve a high resolution of 5 ps and a wide delay range of 8.6 ns simultaneously. It does so by combining elements of digital and analog delay locked loops and uses a replica circuit to compensate for temperature variations. Furthermore, accurate and precise delay steps with 3.8 ps RMS jitter are obtained by using combinatorial redundancy. Its overall performance is superior to state-of-the-art approaches, which make a trade-off for at least one of the performance metrics.