A 0.2–2.5 GHz CMOS power amplifier using transformer-based broadband matching network

A 0.2∼2.5 GHz broadband CMOS power amplifier (PA) for a wireless transceiver is designed using 180 nm CMOS process. Considering the difficulty of integration, this PA is divided into a high-band PA (1.2∼2.5 GHz) and a low-band one (0.2∼1.2 GHz). The high-band PA achieves all components integrated on-chip by using transformer-based matching network and the low-band one adopts off-chip matching network in order to obtain optimal performance. The S11 of the PA is less than −10 dB and the maximum S21 achieves 15.13 dB at 0.5 GHz. From 0.2 GHz to 2.5 GHz, the PA shows a maximum output power of 22.42 dBm, a peak power added efficiency (PAE) of 23.3 % and the power gain more than 10.44 dB. When the input power is less than 0 dBm, the IMD3 is decreased blow −25 dBc. The total chip size of the PA is 1.23×1.96 mm 2 and it consumes 230 mA from the 3.3 V supply voltage.