A specialized programming language for coordinating software execution timing in embedded systems

We have developed Representation and Implementation of Temporal Event Sequences (RITES), a domain specific programming language which enables users to precisely specify how software and firmware execute with respect to real time on embedded systems hardware. Precise timing of software and firmware operations is critical to many functions within a space system, including coordination of hardware components, scheduling of spacecraft resources, and execution of communications protocols. RITES provides a highly expressive and precise mechanism to specify when software and firmware operations occur. The programming languages commonly used to develop the software and firmware for space systems (i.e. C, C++, and Verilog) do not have a built-in semantic concept of time. In contrast, RITES allows the specification of scheduled behaviors to be made and modified using concepts natural to the scheduling problem and with a compact, intuitive syntax. RITES components coordinate the activities and temporal behavior of other modules within the system rather than encapsulating complete system behavior. The RITES language is supported by a family of code generators that produce executable implementations of RITES programs. Code generators translate RITES programs to C functions for execution as software on sequential processors and to Verilog hardware description language (HDL) modules for execution within Field Programmable Gate Arrays (FPGAs). Additional code generators produce HDL implementations with error tolerance features allowing execution on FPGAs susceptible to single event effects (SEEs) in environments with significant radiation. Specifically, RITES modules may be automatically implemented as Verilog with local or distributed triple modular redundancy (TMR). We provide several examples of the implementation of precision timed behavior at various timing granularities, including clock-by-clock control of a digital signal processing (DSP) core within an FPGA for efficient execution of signal processing applications, implementation of a time division multiple access (TDMA) radio communications protocol, and a detailed study of the configuration and control of an external image compression ASIC.