Dynamic Read VMIN and Yield Estimation for Nanoscale SRAMs

The design and verification process for SRAMs can be long and tedious due to the very large multi-dimensional design-space and the large computational time of Monte-Carlo (MC) simulations. In this work, we propose a fast analytical model, which takes into account the supply-voltage, temperature, process-variations, and array-design variables to characterize the critical read path and the small signal differential sensing and then evaluates the read-access failure probability and the corresponding VMIN and yield. With a low evaluation time of 15 seconds and < 6% error, the model is used to evaluate ~ 160K different SRAM designs in 20 hours. The results of the dataset are used to analyze the effect of key design-variables on yield and performance, determine inter-variable correlation, and calculate feature importance. In particular, important statistical results about sense-amplifier-enable timing and dynamic behavior of frequency correlation are presented in this work. Thus, the method can be very useful for SRAM designers to quickly calculate design feasibility and analyze the design space to optimize power, area, and speed.