Low-Power Area-Efficient Decimation Filters in Sigma-Delta ADCs

The performances of different structures for Sine filters were analyzed and compared in this paper. To reduce their power consumption and chip area, a new optimum method was proposed. And it was implemented in poly-phase structure and direct-realization structure respectively for verification. In addition, the low-power area-efficient optimization scheme for decimation filters in Sigma-Delta ADCs was also discussed. All simulation results were obtained under supply voltage of 1.62 V using TSMC 0.18 mum CMOS technology. The results showed that, compared to CIC, 36% area and 50% power were saved for poly-phase structure and 64% power consumption was reduced for direct-realization structure.