Voltage Coupling Enhancement for Transient Gate Overvoltage Suppression of Insulated Gate Trigger Thyristor in Ultrahigh di/dt Pulse Applications

In this article, a voltage coupling enhancement (VCE) technique is developed to suppress the transient gate overvoltage of an insulated gate trigger thyristor (IGTT) in ultrahigh di/dt pulse applications. It is found that, due to the gate–cathode voltage ( VG – VC ) coupling associated with the intrinsic gate–cathode capacitor ( Cgc ) and inevitable common source inductance ( LC ) of IGTT, the gate voltage ( VG ) would oscillate with the cathode voltage VC (= LC  ×  di/dt ), which produces high gate–cathode voltage ( VGC ) oscillation. This easily leads to device failure especially at high di/dt pulse condition. Enhanced VG  −  VC coupling by increasing intrinsic Cgc can contribute to the close following of VG against VC , suppressing the transient gate overvoltage. Thus, a modified dummy gate IGTT (DG-IGTT) structure with increased Cgc is specially designed as a practical implementation of the VCE technique. Experimental results show that the DG-IGTT has a low gate overvoltage ( VGC- max) of 31.2 V, whereas the VGC- max of conventional IGTT is over 136.7 V. In addition, the DG-IGTT in Kelvin source package can further achieve a much lower VGC- max of 18.5 V at ultrahigh di/dt of 32.4 kA/ μ s. The DG-IGTT successfully works at the repetition rate of 200 Hz, indicating the proposed VCE technique is promising for improving device robustness in ultrahigh di/dt and repetitive pulse applications.