A dual-bit split-gate EEPROM (DSG) cell in contactless array for single-Vcc high density flash memories

A new source-side injection Dual-bit Split-Gate (DSG) flash EEPROM cell is designed and characterized. With a 0.6 /spl mu/m process, the cell-size of 1.95 /spl mu/m/sup /spl and//2 per bit in a contactless array is achieved. With a shared select-gate, the cell consists of three directly jointed channels. Taking advantage of the split-gate structure, the threshold voltage of the floating-gate transistor is allowed to move from enhancement-mode to depletion-mode between write and erase operations. Only moderate voltages (less than 10 V) are required the for the cell operations, which relax the high-voltage device requirements on peripheral circuitry and thus simplify the process with less masking steps. With on-chip charge pumps, this cell is suitable for very high density and low power mass-storage applications with single-Vcc power supply. >