Incremental Bitline Voltage Sensing Scheme With Half-Adaptive Threshold Reference Scheme in MLC PRAM

Research on phase-change random access memory (PRAM) for multilevel cells (MLCs) has been actively conducted owing to the advantages of PRAM cells, such as large resistance margin and fast read/write access time. However, the resistance drift (R-drift), which increases the resistance of the PRAM cells with time, should be overcome to achieve MLC PRAM operation. In this paper, we introduce sensing methods with R-drift tolerance, namely, drift-resilient cell-state metric and incremental bitline voltage (IBV), and compare these sensing methods in terms of the sensing margin and read access time. In addition, we propose a sensing scheme for IBV (IBVSS) with a half-adaptive threshold reference scheme (H-ATRS) to achieve high-R-drift tolerance in severe R-drift conditions with a small layout area for the reference cell. Verification of the IBVSS with H-ATRS is performed by HSPICE simulation using the 0.25- $\mu \text{m}$ model parameters used in the peripheral circuit of Samsung’s 20-nm PRAM technology. From the simulation, we find that the IBVSS with H-ATRS achieves more than 1 V of sensing margin under severe R-drift conditions, which ensures stable read operation in the MLC PRAM with 304 ns of sensing time.