Shift register unit, gate electrode driving circuit, and display device

Shift register units (SR1, SR2, SR3, SR4), gate electrode driving circuit, and display device. The shift register units (SR1, SR2, SR3, SR4) comprise two set-reset RS triggers (RS1, RS2). A set terminal S of a first RS trigger (RS1) receives a triggering signal (STV). A reset terminal R of the first RS trigger (RS1) receives a clock signal (CLK). An S terminal of a second RS trigger (RS2) receives the clock signal (CLK). An terminal R of the second RS trigger (RS2) is connected to a Q terminal of the first RS trigger (RS1). A Q terminal of the second RS trigger (RS2) is an output terminal of the shift register units (SR1, SR2, SR3, SR4).