Design of a novel domino XNOR gate for 32 nm-node CMOS technology

A novel domino XNOR gate is designed, using techniques of pn mixed pull-down network and dual-threshold voltage. HSPICE simulation results prove that compared with the standard n-type domino XNOR gate the dynamic power of proposed design can be reduced by 43.9% and the minimum static power is reduced by 86.4%, while enhancing the AC noise immunity by 12.5%.