Optimal Design of Monolithic Integrated DC-DC Converters

Increasing supply current of high-performance microprocessors and limited real-estate available for power delivery in mobile platforms have spurred research of monolithic integrated DC-DC converters. Based on a model for the three key power loss mechanisms we derive an analytical solution for the optimal DC-DC converter design, linking power efficiency directly to CMOS front-end parameters and inductor technology. Further analysis shows that source-drain leakage, skin effect, eddy currents, and routing parasitics, although significant, don't change the optimal design.