Power Optimization Opportunities for a Reconfigurable Arithmetic Component in the Deep Submicron Domain

In the era of deep submicron integration, digital design complexity is increasing with rates that are hard to follow. On one hand, market demand for newer, faster and reliable applications never stops. On the other hand, fabrication technology can not cover this demand with frequency increase and dimension shrinking only, as it has been done in the past. New architectural level innovations are needed, like reconfigurable computing. Reconfigurable computing takes advantage of idle components or shared functionality between different algorithms, to maximize utilization and improve performance, based on efficient circuit switching interconnections. However, dense and switching interconnections bring power dissipation problems, which are more clear in the deep submicron domain. This paper, presents opportunities for both dynamic and static power reduction for a reconfigurable arithmetic component, which can be used as an IP in RTL and above RTL synthesis methodologies (ESL, HLS, IP based). Both bitwidth and technology scaling is explored, showing that the overall proposed architecture offers clear advantages as device dimensions shrink.