Early assessment of tunnel-FET for energy-efficient logic circuits

In this paper, we explore the potentialities of TFET-based circuits operating in the ultra-low voltage regime. We show that the problem of unidirectional transport in 6T SRAMs can be solved by employing outward-facing access-transistors and suitable voltage levels during the read. We propose the level shifter as a key application domain of the hybrid TFET-MOSFET deployment strategy. By using the full adder as a benchmark vehicle, we observe that III–V TFETs will allow for a much better energy efficiency than future 10 nm node CMOS FinFETs at low VDD.