Development of an IEC test for crystalline silicon modules to qualify their resistance to system voltage stress

IEC 62804 Ed. 1, System voltage durability qualification test for crystalline silicon modules, is being developed. First, two module designs are compared in chamber and in the natural environment of Florida (USA). From these results, a stress level of 60 °C, 85% relative humidity, a bias of nameplate system voltage, 96 h dwell, and a pass/fail limit of 5% relative power degradation at 25 °C and 1000 W/m2 irradiance is initially proposed for the draft protocol. This paper next focuses on one of the main controversies within the development of this standard—the use of damp heat in an environmental chamber versus a conductive foil to complete the circuit to ground during the test. Conventional 60-cell multicrystalline silicon modules with (i) a standard aluminum frame, (ii) a modified frame, and (iii) a rear rail design were tested for potential-induced degradation (PID). These three module designs were stressed at the draft protocol conditions stated above and outdoors, applying negative system voltage bias during hours of daylight to simulate array voltage. The damp heat environmental chamber tests run according to the protocol distinguish the relative resistance of five module designs to PID in the field and correctly rank-order the durability in the field to the extent tested (up to 28 months). Finally, the degradation rate is determined at 25 °C using a foil to ground the module face on a subset of modules susceptible to PID, and the results with respect to measured field performance of the modules are discussed. Copyright © 2013 John Wiley & Sons, Ltd.