Efficient hardware implementations of QTL cipher for RFID applications

Extensive deployment of ubiquitous computing devices brings wide range of privacy and security issues in the low-resource domain. Various lightweight algorithms are proposed to solve security problem for these resource-constrained environments. In this work, optimised hardware implementations of lightweight block cipher QTL are proposed in order to provide security with optimum resource utilisation. In proposed reduced datapath architecture, resource utilisation is reduced and it gives good trade-off between area and performance. In proposed pipelined architecture, encryption round is divided into two sub-stages. This design methodology significantly improves the operating frequency. As a result, this design is apt for high-speed applications. Moreover, the proposed unified architecture combines three key scheduling designs into single design for QTL encryption and provides flexible security. All three architectures are extensively evaluated and compared on the basis of performance, area utilisation, energy requirement and power consumption for their implementations in different FPGA platforms.