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A 3V 1T1C 1Mbit FRAM with a Variable Reference Bitline Voltage Scheme and Double Wordline Pulse Scheme
A 3V 1T1C 1Mbit FRAM with a Variable Reference Bitline Voltage Scheme and Double Wordline Pulse Scheme
1999
Yoshiaki Takeuchi
Sumio Tanaka
Yasuo Itoh
Tadashi Miyakawa
Ryu Ogiwara
S Mano Doumae
Hiroyuki Takenaka
Iwao Kunishima
Susumu Shuto
Osamu Hidaka
S. Ohtsuki
Tanaka Shin-ichi
Keywords:
Electrical engineering
Physics
Voltage
Voltage reference
Pulse (signal processing)
Correction
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