CEPA: CNN-based Early Performance Assertion Scheme for Analog and Mixed-Signal Circuit Simulation

The design and verification of analog and mixed-signal (AMS) circuits typically involve many time-consuming simulations to qualify target specifications or optimize the design parameters for better performance. The long simulation time significantly slows down the speed of optimization iterations for both human designers and automatic AMS optimizers, inevitably resulting in high design costs and less-optimized designs. In this work, we propose a convolutional neural network (CNN)-based early performance assertion (CEPA) scheme to identify designs with unsatisfactory performance quickly and accurately. Thanks to the feature extraction capability of CNN, CEPA only requires a short duration of transient waveform to predict the satisfaction of the target specifications for a certain design that is otherwise obtained by a long transient simulation. In addition, applying the fine-tuning technique to the proposed CEPA scheme can further extend the inference from schematic-level simulation to post-layout simulation with only a few training samples (i.e., enhancing CEPA's usage with a low training cost). A sample-and-hold circuit and a delta-sigma digital-to-analog converter are presented to prove the effectiveness of the proposed CEPA scheme. With its maximum assertion accuracy of 99%, CEPA reduces the simulation time for assertion by orders of magnitude.