Printability verification function of Mask Inspection System

ABSTRACT In addition to the conventional demands for high sensitivities with which the mask inspection system detects the minute size defects, capability to extract true defects from a wide variety of patterns that should not be counted as pseudo defects has been quite demanding. It is necessary to ascertain suppression of MEEF incurred by the combination of parameters such as LER and defects of SRAF. NFT and Brion are jointly developing a mask-image based printability verification system with functions combining their respective technologies with the results from ASET’s res earch. This report describes such defect detection results and introduces the development of a mask inspectio n system with printability verification function. Keywords: Mask Inspection System, Printability, Lithography, aerial image, resist image, simulation, pseudo defects, NPI-6000 1. INTRODUCTION In an effort to continue the utilization of ArF lithography and exploit its maximum performance capability, various schemes such as OPC and SRAF have been added to mask layouts. The demand for making minute features on masks has become so great that the limits of the precision of pattern size, edge roughness, and defect size have almost become same. In addition to the conventional demands for high sensitivity with which the mask inspection system detects the minute size defects, capability to extract true defects from a wide variety of patterns that should not be counted as defects (pseudo/nuisance defects) has become more challenging. It is particularly necessary to ascertain suppression of MEEF incursion caused by factors such as combination of edge roughness of a main pattern and defects of SRAF. In order to deal with such situations, a new method to dete ct defects using simulated wafer aerial images and wafer resist images is being developed. For such purpose, capabilities for getting precise mask images, and doing high-speed-and-high-accuracy calculations have become indispensable. As shown in figure 1, Association of Super-Advanced Electronics Technologies (ASET), Japan, has started a 4-year project to reduce the mask manufacturi ng cost and turn-around-time (TAT) by th e optimization and integration of mask data processing (MDP), mask writing, and mask inspection with support from the New Energy and Industrial Technology Development Organization (NEDO), Japan. The project was launched in 2006. A printability verification function is one of the themes of the program, and ASET has been evaluating Brion’s Lithography Manufacturability Check (LMC) technology as a possible ca ndidate to be employed for the task.