Session 14 overview: Digital PLLs and SoC building blocks: High-performance digital subcommittee

The nine papers in this session highlight developments in clock generation, sensors, and security. Digital PLL solutions are presented in FinFET technology, improved power supply noise and jitter, and synthesized fractional-N functionality. Papers in this session also present solutions for on-die power and aging sensors for reliable operation, and address security with innovations in device authentication using physically unclonable functions.