Mapping Parameterized Dataflow Graphs onto FPGA Platforms

Abstract Dynamic reconfiguration in digital systems provides valuable flexibility and opportunities for enhanced efficiency, but also leads to increased complexity in terms of design analysis and optimization. Existing approaches focus primarily on either abstract models with the capability of expressing dynamic reconfiguration at a high level or techniques for low-level, platform-specific implementation. While both of these areas of advancement are important, there is an increasing need to bridge the gap between them in order to better realize the potential of dynamic reconfiguration technology. In this paper, we provide background on relevant methods for application modeling, and platform-based implementation of dynamically reconfigurable signal processing systems. To help bridge the gap between these groups of methods, we develop new methods based on an application modeling formalism called parameterized dataflow , along with techniques for mapping parameterized dataflow specifications onto FPGA architectures. Our proposed parameterized dataflow approach for design and implementation of dynamically reconfigurable signal processing systems provides a comprehensive framework that encompasses application modeling, task scheduling, and hardware mapping. We demonstrate our methods using case studies in the domains of wireless communication and computer vision.