An analysis of offset calibration based additional load capacitor imbalance for two-stage dynamic comparator

An intentional load capacitor imbalance can be used to calibrate the offset of a dynamic comparator. For a two-stage dynamic comparator, this additional imbalance load capacitor can be either added in the first stage or added in the second stage. This paper analyses this effect of the intentional load capacitor imbalance for the two cases. The input-referred offset voltage due to the imbalance load capacitor is derived, which is used to compensate the intrinsic offset of the comparator. This analytical work provides a theoretical basis for calibrating the total input-referred offset of a two-stage dynamic comparator based additional load capacitor imbalance. In addition, a simple and effective calibration algorithm is proposed. The two-stage dynamic comparator with calibration circuit is implemented in 0.18μm CMOS process. The simulation results show that the total input-inferred offset decreases significantly after calibrating.