Overlay Accuracy Investigation for advanced memory device

Overlay in lithography becomes much more challenging due to the shrink of device node and multi-patterning approach. Consequently, the specification of overlay becomes tighter, and more complicated overlay control methods like high order or field-by-field control become mandatory. In addition, the tight overlay specification starts to raise another fundamental question: accuracy. Overlay inaccuracy is dominated by two main components: one is measurement quality and the other is representing device overlay. The latter is because overlay is being measured on overlay targets, not on the real device structures. We investigated the following for accurate overlay measurement: optimal target design by simulation; optimal recipe selection using the index of measurement quality; and, the correlation with device pattern’s overlay. Simulation was done for an advanced memory stack for optimal overlay target design which provides robustness for the process variation and sufficient signal for the stack. Robustness factor and sufficient signal factor sometimes contradicting each other, therefore there is trade-off between these two factors. Simulation helped to find the design to meet the requirement of both factors. The investigation involves also recipe optimization which decides the measurement conditions like wavelength. KLA-Tencor also introduced a new index which help to find an accurate measurement condition. In this investigation, we used CD-SEM to measure the overlay of device pattern after etch or decap process to check the correlation between the overlay of overlay mark and the overlay of device pattern.