Delay-based Phase-Locked Loop Parameters Design based on Stability Region of Grid-Connected Single-Phase Inverter under Grid Voltage Sags

For the grid-connected inverter, grid voltage sag can be a typical phenomenon. From the prospective of safe and robust operation, the inverter should be stable when the grid voltage sag (or large disturbance) occurs. Although the inverter stability in this case has attracted considerable attentions, few studies have given suggestions on the system stability boundary and parameter design. To fill this gap, this paper deeply discusses the large-signal stability of the system under different situations and reveals the quantified impact of the phase-locked loop (PLL) on the large-signal stability of the system based on the fundamental current-source model. The large-signal stability criterion and boundaries for grid voltage sags are established, which are instructive to the design of PLL parameters. Besides, a novel design guideline for the PLL parameters is proposed to ensure the robust operation of the system both under the steady-state and grid voltage sags, as well as to achieve good dynamic performance after large disturbance occurs. The theoretical, simulation and experimental results show that the proposed stability boundary has a certain accuracy and the PLL parameters design guideline can ensure the system stability both under steady-state and grid voltage sag conditions.