Multi-Channel ADC with Improved Bit Rate and Power Consumption for ElectroCorticoGraphy Systems

A multi-channel ADC structure is presented, which is dedicated to the digitization of multi-channel ECoG signals. The ADC is designed to decompose the signals on all the channels into one shared common baseline component and channel-specific differential components containing channel activities. The baseline component is digitized using a low-resolution ADC (BL-ADC), and the differential channel activities are converted to digital using a time-multiplexed sub-ADC. Designed to benefit from the spatial redundancy that exists in the common baseline signal, the proposed structure exhibits low power consumption and small silicon area. Another advantage of the proposed ADC scheme is the reduction achieved in the extent of the output digital data. This is because of sharing the common baseline data among all the channels. Fully-integrated version of the 8-channel ADC was designed in a 0.18-µm CMOS process, occupying about 0.015 mm2 of silicon area. Operating at a supply voltage of 1.8 V, sampling frequency of 1 kS/s for BL-ADC and 8 kS/s for the time-shared sub-ADC, the entire circuit dissipates 0.82µW.