A Conversion Mode Reconfigurable SAR ADC for Multistandard Systems

A single-channel reconfigurable successive approximation register (SAR) analog-to-digital converter (ADC) is presented, which features its speed expanding with conversion mode. The reconfigurable capacitor digital to analog converter (CDAC) is proposed to achieve multiple conversion modes without wasting capacitance. In 1-b/cycle conversion mode, the proposed ADC can achieve the sampling rate of 60-Ms/s and 9-b resolution. Based on the 2-b/cycle conversion mode, the proposed ADC can double the sampling rate and be reconfigured as a 120-MS/s, 8-b converter. Besides, the detection skip algorithm and charge sharing technology are involved to remove the precharge operation time and reduce the switching energy consumption. Moreover, the control logic is optimized to minimize the chip area and matches the reconfigurable characteristics well. A prototype ADC is fabricated in the 180-nm standard CMOS process, which achieves the 54.1-/46.7-dB signal-to-noise-plus-distortion ratio (SNDR) at 60-/120-MHz sampling frequency with the power consumption of 1.9/3.5 mW. The prototype ADC achieves a peak figure of merit (FoM) of 77-fJ/Conv.step at 2-b/cycle conversion mode. The ADC core occupies an active area of only 0.12 mm2.