Device architecture and reliability aspects of a novel 1.22 µm 2 EEPROM cell in 0.18 µm node for embedded applications

The device architecture and operation conditions of a novel 1.22 µm2 EEPROM cell in 0.18 µm technology node have been revealed. With such a novel cell, the traditional scaling barrier of FLOTOX EEPROM cell has been broken. Reliability aspects of such a cell and the related memory matrix have been extensively studied: the cell endurance. programming and erase disturbs, the stress induced leakage current in the cells, the reliability of sector select gates and the reliability of byte-select gates.