A Supply Noise Compensation Circuit for Clock Buffers to Reduce Timing Jitter

This paper introduces a supply noise compensation circuit for low voltage, low timing-jitter clock distribution networks. To suppress supply noise induced jitter, sensing circuit with opposite sensitivity is proposed to compensate the invertor transition variations. Both of the static and low frequency dynamic supply noise induced-jitter can be suppressed. The design is verified in a 1.2GHz time-interleaved ADC on 40nm CMOS technology and consumes 2mW from a 1.8-V supply. The measurement results show that the clock peak-to-peak and rms jitter are improved from 10.64ps and 1.17ps to 8.6ps and 0.87ps by 2.04ps and 0.3ps respectively. The proposed supply noise compensation is compatible with other supply noise compressing technique to improve the jitter performance in clock distribution networks.