Research on Dual-Core Lock Step Mechanism and Its Application for Commercial High Performance APSoC

With the rapid development of commercial satellites, the APSoC devices with the advantages of low cost, superior performance, high integration, and easy acquisition have become an important way to improve satellite performance and reduce satellite development cost. However, with the continuous reduction of the process size of this kind of device, among many radiation effects, the soft error caused by single event upset is an important factor threatening the reliability of the circuit. In this work, a Dual-Core Lock Step mechanism for commercial high performance APSoC is developed and proposed for mitigation of soft errors by SEU. Within the APSoC, the output of the two CPUs is periodically compared by the Checker module. When the outputs of the two CPUs are different, these two processors will be set to the last stored correct statue so that the system can recover from an error. This method can improve the ability of APSoC devices to deal with soft errors caused by SEU. A Markov process is used to analyze the reliability of DCLS mechanism. The model is simulated and tested by MATLAB. The results show that the reliability and mean time between failures of the DCLS technology meet the life requirements of low orbit satellites.