A HARDWARE IMPLEMENTATION OF THE APE100 ARCHITECTURE

A. Bartoloni,G. Bastianello,C. Battista,S. Cabasino,F. Marzano,Pier Stanislao Paolucci,J. Pech,F. Rapuano,Emanuele Panizzi,R. Sarno,Gian Marco Todesco,M. Torelli,W. Tross,P. Vicini,N. Cabibbo,A. Fucci,R. Tripiccione

A HARDWARE IMPLEMENTATION OF THE APE100 ARCHITECTURE

1993

A. Bartoloni
G. Bastianello
C. Battista
S. Cabasino
F. Marzano
Pier Stanislao Paolucci
J. Pech
F. Rapuano
Emanuele Panizzi
R. Sarno
Gian Marco Todesco
M. Torelli
W. Tross
P. Vicini
N. Cabibbo
A. Fucci
R. Tripiccione

APE100 processors are based on a simple Single Instruction Multiple Data architecture optimized for the simulation of Lattice Field Theories or other complex physical systems. This paper describes the hardware implementation of the first APE100 machine.

Keywords:

Computer architecture
SIMD
Lattice (order)
Computer hardware
Architecture
Physical system
Lattice field theory
Theoretical computer science
Computer science

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