CMOS leakage power at cell level

Leakage power consumption in nanometric CMOS circuits is growing at exponential rate due to the aggressive scaling trends of channel lengths, gate oxide thickness and doping profiles. In this paper the analysis and characterization of leakage currents and the corresponding leakage power is studied at cell level. A characterization methodology is discussed and applied to inverter, NAND and NOR cells using the Berkeley predictive technology model BPTM for BSIM 4.50 and HSPICE. The simulation results for 65, 45 and 32nm CMOS performed in these cells show the high dependence of leakage power on the circuit state and the increasing impact of gate leakage on the variability of the total leakage of the cell