2D compact modeling of the threshold voltage in triple- and Pi-gate transistors

Multiple-gate transistors are considered as very promising candidates for the 22 nm technological node. They are named Triple-gate FETs (TGFETs, [1]) when the gate controls three sides of the silicon body (figs. 1 and 2); if the channel etch process step penetrates in the Buried Oxide (BOX), the transistor is named Pi-gate FET ([2], fig. 2). There is currently a strong need for compact models of such architectures, in order to evaluate their circuit performance. In this work, the threshold voltage modeling of long channels TGFET and Pi-gate FET is studied.