Top-gate thin-film transistor, array substrate and manufacturing method therefor, and tft device

Provided is a top-gate thin-film transistor (10), which aims to solve the problem in the prior art that damage to a semiconductor when source-drain metal etching is prevented using a passivation layer. The top-gate thin-film transistor (10) comprises a first conducting layer (11), an active layer (12), an insulation layer (13) and a second conducting layer (14) which are formed in sequence,wherein the first conducting layer (11) comprises source electrodes (112) and drain electrodes (114) which are arranged at intervals, a channel (116) being sandwiched between the source electrodes (112) and drain electrodes (114); the active layer (12) comprises a semiconductor layer (122) arranged in the channel (116) and having two ends respectively overlapped at the top of the source electrodes (112) and the drain electrodes (114), and a protective layer (124) adhered to the semiconductor layer (122); the insulation layer (13) comprises a gate insulation portion (132) located on the protective layer (124) and the source electrodes (112) and drain electrodes (114); and the second conducting layer (14) comprises a gate portion (142) located on the gate insulation portion (132) and arranged relative to the channel (116). Using the protective layer (124) to protect the semiconductor layer (122) avoids the influence of the gate insulation portion (132) on the semiconductor layer (122). In this way, a dense gate insulation layer is used to play a role of passivation without adding an additional passivation layer, thereby simplifying the process steps.