A 12-bit 2-GS/s Pipelined ADC Front-end Stage with Aperture Error Tuning and Split MDAC

A 12-bit 2-GS/s pipelined analog-to-digital converter (ADC) front-end stage in 28 nm process is presented. Sample-and-hold amplifier-less (SHA-less) structure is adopted to avoid additional noise, nonlinearity, and power. Aperture error tuning is presented to mitigate the inherited problem of the SHA-less structure. New split closed-loop multiplying digital-to-analog converter (MDAC) structure and 1.2 V dual- input amplifier is used to lower the power and to enhance the speed. Dithering is adopted and comparator threshold voltage dithering is modified for low supply voltage and higher speed. Simulation shows a 66.4 dB signal-to-noise-and-distortion ratio (SNDR) and 76.1 dB spurious-free dynamic range (SFDR) under 1.38 GHz input frequency. The wideband input range and the aperture error tunability are proven by the simulation. The 163.8 dB Schreier figure-of-merit (FoM) and 52.2 fJ/conv.-step Walden FoM is achieved based on an assumed 180 mW total power, of which 90 mW is consumed by the front-end stage.