FPGA Investigation on Error-Flare Performance of a Concatenated Staircase and Hamming FEC Code for 400G Inter-Data Center Interconnect

Forward error correction (FEC) performance down to 10 −15 bit error rate (BER) of a concatenated staircase and Hamming code (CSHC), which was recently proposed for the first 400G inter-data center interconnect standard, is verified with a 50-piece field-programmable gate array (FPGA) implementation at a record 200-Gb/s throughput. The effect of digital noise tail accuracy on the FEC emulation results is investigated. A converging criterion is proposed and demonstrated for achieving high confidence in artificial digital-noise-source-based FPGA emulations. The CSHC performance as a function of decoding iterations of the outer staircase code is investigated, and emulation results show that six staircase decoding iterations is the optimal choice. The FPGA emulations also reveal the existence of an error flare of the CSHC at 10 −10 BER, which corrects the predicted BER threshold from 1.25 × 10 −2 to 1.21 × 10 −2 . Further investigations on the effects of interleaving processes and staircase decoding buffer size show that the error flare behavior of the CSHC depends on the decoding buffer size of the outer staircase code. To remove the CSHC error flare, a proper choice of the staircase decoding buffer size is shown to be 6, which also moves the FEC threshold to 1.27 × 10 −2 .