Large array EMCCD driving circuit design

Large-array EMCCD requires a complex and large number of drive signals. To solve this problem, this paper designs a large-array EMCCD drive circuit system, which uses large-scale integrated circuit FPGA to generate EMCCD’s timing signal, multiplication signal and DC bias signal, using Verilog language for hardware description, and using the integrated AD chip to sample the analog output signal of EMCCD. Then use the idea of "ping-pong" operation to control DDR3 to complete the splicing of multi-channel digital images. Finally, based on the KAE-02150 EMCCD chip produced by ON Semi, the design of a large-area internal line transfer EMCCD camera was realized.