High-Throughput Multi-Frame Decoding of QC-LDPC Codes with Modified Rejection-Based Minimum Finding
2021
The key computation in the min-sum decoding algorithm of a
Low-Density Parity-Check (LDPC) code is finding the first two minima and also
the location of the first minimum among a set of messages passed from Variable
Nodes (VNs) to Check Nodes (CNs) in a Tanner graph. In this paper, we propose a
modified rejection-based scheme for this task which is able to find the one-hot
sequence of the minimum location instead of its index. We show that this
modification effectively reduces the complexity of min-sum decoding algorithm.
Additionally, we reveal a pipelining potential in such a rejection- based
architecture which facilitates the multi-frame decoding of LDPC codes and
therefore results in improvement in decoding throughput with bearable hardware
overhead. Synthesis in an industrial 28nm CMOS technology shows improved
results in terms of throughput, power, and chip area.
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