Memory-efficient architecture for FrWF-based DWT of high-resolution images for IoMT applications

This paper proposes a simple low memory architecture for computing discrete wavelet transform (DWT) of high-resolution (HR) images on low-cost memory-constrained sensor nodes used in visual sensor networks (VSN) or Internet of Multimedia Things (IoMT). The main feature of the proposed architecture is the novel data scanning technique that makes memory requirement independent of the image size. The proposed architecture needs only (30S) words of memory, where S is the number of parallel processing units and a critical path delay (CPD) equal to the delay of a multiplier (Tm). Furthermore, a multiplierless version of this architecture is also proposed which reduces the CPD to Ta

Keywords:

• Memory architecture
• Multiplier (economics)
• Adder
• Field-programmable gate array
• Wireless sensor network
• Discrete wavelet transform
• Computer science
• Computer hardware
• Digital signal processing
• Lookup table

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