Timing correlation between clock & data strobe with dynamic rank switching in DDR3 RDIMMs

Memory plays a significant role in successful operations of modern day servers. DDR3 memory has been around for a while and the next generation is almost available. There are lots of challenges which still exist and are not fully uncovered with the DDR3 based ISRDIMMs and discussed in this paper is a unique problem faced during the server memory characterization of ISRDIMMs. Issues were unearthed in timing relationship between the Clock and WR DQS in a multi-Rank DIMM and experiments were conducted to find a suitable solution. The proposed solution uses a Built-In-Self-Test engine to toggle the phase rotator attached to a particular bit to overcome the zero timing margin issues. Experiments were conducted with single and multi-Rank DIMMs, sequential & random DATA pattern and with different addressing schemes to root cause the problem and ensure the proposed solution works fine in all cases.