A framework for yield modeling and yield enhancement in integrated circuit design and fabrication

This dissertation is focussed on developing new approaches for defect and yield modeling and yield enhancement. The research is inspired by the continuing trend of feature size reduction and chip area increments in integrated circuit (IC) manufacturing. A hierarchical taxonomic system for process defects is constructed. The taxonomic system possesses both predictive and explanatory powers, and is therefore a versatile tool in defect and yield modeling and yield enhancement. In defect modeling, a framework for modeling inter-layer and intra-layer short-circuits and intra-layer open-circuits due to three-dimensional spot defects is proposed. The main feature of this framework is parametrization of open-circuits from the viewpoint of conductor's resistance, thereby allowing accurate estimations of defect sensitive regions in ICs. A yield model based on generalized Poisson statistics is developed to offer a natural explanation for the presence of defect clusters on integrated circuit chips and wafers. Also, several measures for empirical evaluation of spatial properties of defect patterns on wafers are proposed. Finally, a Design-for-Yield methodology at the layout synthesis level in IC design is proposed. The focus is on improving routing solutions in terms of layout critical area reduction against short-circuits due to spot defects.