High-Speed Parallel Implementation of AES Key Expansion Algorithm Based on FPGA

According to the traditional AES algorithm, we present an optimized scheme, which offers an implementation of AES key expansion algorithm. The key expansion algorithm is shown by matrix in this scheme, then it is converted to look-up table, we use FPGA which has rich look-up table and storage resources to implement algorithm in parallel. The scheme reduces the complexity of the algorithm. As can be seen from experimental results, according to the needs of the encryption system, the system data processing speed and data throughput can be changed in real-time by changing the system clock.