Rearranging Random Issue Queue with High IPC and Short Delay

Single-thread performance has remained mostly static for more than a decade. Among structures in a processor, the issue queue (IQ) is a structure that significantly affects the performance. To achieve high performance, high IPC and a short delay are required for the IQ, which have failed to be achieved in conventional IQs. We propose a novel IQ organization that we call the rearranging random issue queue (RRQ). The RRQ realizes an age-aware instruction selection in the IQ where instructions are ordered randomly. The RRQ divides the IQ into small (OQ: old queue) and large portions (MQ: main queue), where instructions in the OQ are prioritized using a simple select logic. To achieve age-aware selection, a small number of the oldest instructions in the MQ are moved to the OQ every cycle. Our implementation of the RRQ does not complicate the IQ circuit, and hardly increases the delay of the IQ. Evaluation results obtained in architectural simulation show that the RRQ achieves IPC as high as the shifting queue with compaction that realizes the perfect age-aware selection. Our evaluation results also show that the performance of the RRQ significantly outweighs that of processors with an IQ that has the age matrix, which suffers a long delay of the IQ.