Multi-chip implementation of a high-speed sorting engine based on rank-ordering

A multi-chip-module (MCM) implementation of a binary sorting engine is presented. Previously, a bit-serial sorter architecture was proposed, which is able to sort up to 63 16-bit numbers in 78 clock cycles, which includes the time spent for the serial data input. This architecture was put on silicon, using a conventional 0.35 /spl mu/m technology, resulting in an area of 13 mm/sup 2/ and an operation at a clock frequency of approximately 200 MHz. The proposed sorting engine consists of individual sorter units and a control block, which takes care of the data transfer between these units.