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Management of Power and Performance with Stress Memorization Technique for 45nm CMOS
Management of Power and Performance with Stress Memorization Technique for 45nm CMOS
2007
A. Eiho
Tomoyuki Sanuki
Eiji Morifuji
Takeshi Iwamoto
G. Sudo
K. Fukasaku
Katsuhiro Ota
T. Sawada
O. Fuji
H. Nii
M. Togo
Kazunori Ohno
Kazuya Yoshida
Hitoshi Tsuda
Toshihiro Ito
Yoshimitsu Shiozaki
N. Fuji
Hiroshi Yamazaki
Mitsuru Nakazawa
Shigeaki Iwasa
Shogo Muramatsu
Kenichi Nagaoka
Masayuki Iwai
Masafumi Ikeda
Masato Saito
Hiroshi Naruse
Y. Enomoto
Kitano
Shuichi Yamada
Koji Imai
Naoki Nagashima
Tomoyuki Kuwata
Fumitomo Matsuoka
Keywords:
Memorization
Electronic engineering
CMOS
Computer science
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